1. Field of the Invention
The present invention relates to a method of fabricating a micro inertia sensor, in which thick silicon bonded to glass is processed at a high section ratio.
2. Description of the Related Art
Electrostatic capacity micro inertia sensors are being actively researched and developed. Acceleration sensors have already been manufactured and merchandised, and gyroscopes have been completed in research and development and has entered the initial steps of commercialization. Hence, present research and development into inertia sensors is directed in directions of increasing the reliability and performance and lowering the price. In order to achieve the research and development directions, the area of an inertia sensor measured must be large, and the inertia sensor must be solid on virtue of a high stiffness of a fine structure. Also, the fabrication method of an inertia sensor must be simple.
One method being used up to now in accordance with this trend is a method of fabricating inertia sensors using silicon bonded to glass as shown in FIGS. 1A, 1B and 1C. This method is disclosed in U.S. Pat. No. 5,492,596, and will now be described with respect to FIGS. 1A through 3B.
First, as shown in FIG. 1A, when a silicon wafer 100 is bonded to glass, it is etched by about 2 .mu.m to form a space 102. Then, as shown in FIG. 1B, boron is heavy-doped on the surface of the silicon wafer 100. As shown in FIG. 1 C, a boron-doped silicon surface 104 is etched by reactive ion etching (RIE) forming grades 106. Here, the depth of etching must be slightly deeper than the thickness of the boron-doped silicon surface 104.
In the meantime, as shown in FIGS. 2A through 2C, a multi-metal system 202 is deposited in the grooves 200 with constituent metal layers 210 and 214 metal electrodes 212 and 220, with stand offs 230, are formed on glass.
Next, as shown in FIG. 3A, glass having electrodes thereon is bonded to the silicon doped with boron. Then, as shown in FIG. 3B, a silicon surface 100 doped with no boron is etched by an etchant having different etching speeds depending on the concentration of boron such as EDP, and thus only a boron-doped surface remains.
This fabricating method is complicated, and the depth at which boron is heavy doped is limited. Thus, it is difficult to fabricate a thick (e.g., about 10 .mu.m) structure, and stresses are generated due to the difference in the concentration at which boron is doped. Also, since glass is bonded to silicon in a narrow space, silicon is attached to glass even in the space 102 by a voltage applied during bonding.
In contrast to the above-described method, there is a method of relatively simply fabricating sensors using only single crystal silicon, as shown in FIGS. 4A through 4F. This method, which is generally called single crystal reactive etching and metalization (SCREAM), is disclosed in U.S. Pat. No. 5,198,390.
First, as shown in FIG. 4A, a thermal oxide layer 314 is formed on single crystal silicon 312, and a photoresist pattern is formed by utilizing a photoresist layer 316. Then, as shown in FIG. 4B, the resultant structure is etched by RIE.
Next, as shown in FIG. 4C, a silicon oxide layer 332 is formed on lateral surfaces 324 and bottom surfaces 326. Then, as shown in FIG. 4D, a metal layer 334 is deposited, and a photoresist pattern 338 is formed on the resultant structure. Thus, as shown in FIG. 4E, the metal layer 334 and the oxide layer 332 are partially removed. At this time, the oxide layer and the metal layer on the bottom surfaces of holes engraved by the first RIE are completely removed.
Thereafter, as shown in FIG. 4F, silicon below a structure 354 is etched using a typical silicon isotropic etchant, thereby forming a structure which floats over the bottom.
This method is relatively simple by using only a single crystal line wafer, but also requires two masks. Also, in this method, a metal layer and an oxide layer must be formed on the lateral surface and bottom surface of a narrow and deep groove, and again patterned thereon, so that the section ratio of the etched groove is limited. Therefore, it is difficult to fabricate a structure having a narrow and deep groove. Furthermore, the use of the single crystal line wafer increases the parasitic capacitance upon measurement, and the absence of an etch stop layer upon RIE makes etching to a precise thickness difficult. Thus, the thickness of a structure is entirely non-uniform. Also, the bottom 354 of a beam is also etched by silicon anisotropic etching, thus making it difficult to maintain the thickness of the beam uniform. If no oxide layer is deposited on the upper sidewall 324 of a structure, silicon on the upper portion 354' may be etched while silicon on the bottom portion is etched by silicon isotropic etchant for a long time.